Method of manufacturing a floating gate and method of manufacturing a non-volatile semiconductor memory device comprising the same

ABSTRACT

A method of manufacturing a floating gate provides an enhancement for the efficiencies of electron discharge and injection. First, a conductive pattern, constituting the arefloating gateforeon, is formed on a substrate. A first insulation layer is formed on a sidewall of the conductive pattern, and then a second insulation layer is formed at an upper portion of the conductive pattern in ways that each increase the sharpness of an edge portion where the sidewall and upper portions of the conductive pattern meet. Therefore, electron transference from the floating gate to a control gate is facilitated.

BACKGROUND OF THE PRESENT INVENTION

[0001] 1. Field of the Present Invention

[0002] The present invention relates to a method of forming a floatinggate and to a method of manufacturing a non-volatile semiconductormemory device comprising a floating gate.

[0003] 2. Description of the Related Art

[0004] Semiconductor memory devices are generally divided into volatilesemiconductor memory devices and non-volatile semiconductor memorydevices. In the volatile semiconductor memory device, data stored in thecell is dissipated when power is not applied. However, in thenon-volatile semiconductor memory, stored data in the cell is retainedeven when power is not applied thereto. Because non-volatilesemiconductor memory devices can store data for long periods of time,they are used to meet the current high demand for flash semiconductormemory devices such as EEPROMs (Electrically Erasable and ProgrammableRead Only Memories).

[0005] Meanwhile, flash semiconductor memory devices can be generallycategorized as stacked flash semiconductor memory devices and split gateflash semiconductor memory devices. The split gate type of flashsemiconductor memory device has a structure wherein a floating gate anda control gate are separated from each other, and the floating gate iselectrically insulated from the outside. Information is stored in amemory cell of the split gate type of flash semiconductor memory deviceusing the yprinciple that current in a memory cell changes depending onelectron injection (programming)/electron discharge (erasing) into/fromthe floating gate. In the electron injection, hot electrons are injectedinto the floating gate by a channel hot electron injection (CHEI)mechanism. The electron discharge is accomplished by Fowler-Nordheim(F-N) tunneling through a tunnel insulation layer between the floatinggate and the control gate of the split gate type of flash semiconductormemory device. In connection with the electron injection (programming)and electron discharge (erasing), a voltage distribution may beexplained as an equivalent capacitor model. Recently, the split gatetype of flash semiconductor memory device has been widely used for thepurpose of storing data.

[0006] The efficiency of the split gate type of flash semiconductormemory deviceeasy transferenceis required depends on the ease in whichelectrons can be transferred from the floating gate to the control gate.Therefore, various research into the structure of the floating gate aimsat improving the efficiency of electron transference in the hope ofrealizing a floating gate having a small cell and, in turn, anon-volatile semiconductor memory device having lower power consumption,and an excellent ability to be integrated with a logic device.

[0007] For example, U.S. Pat. No. 5,029,130 discloses a method ofmanufacturing a floating gate capable of promoting the transference ofelectrons from the floating gate to a control gate. The method entailsoxidizing an upper portion of the floating gate to increase thesharpness of the edge of the floating gate. However, the sharpness isincreased only at the upper portion of the floating gate. Accordingly,the speed at which electrons can be transferred from the floating gateto the control gate is still rather limited.

[0008] Korean Laid-Open Patent Publication No. 2001-91532 discloses amethod of manufacturing a split gate type of flash semiconductor memorydevice in which a gate oxide is formed on a silicon substrate, and thena polysilicon layer and a nitride layer are sequentially formed on thesubstrate including over the gate oxide. The nitride layer isselectively etched by a photolithographic process to form a nitride maskpattern. Then, an oxide layer is formed on the polysilicon layer. Thepolysilicon layer and the nitride mask pattern are removed by etching toleave a portion of the polysilicon layer beneath the oxide layer. Afteran interpoly tunnel insulation layer is formed, a control gate is formedon the oxide layer, the interpoly tunnel insulation layer and the gateoxide. Impurities are implanted between the polysilicon layer and theoxide layer to form source/drain regions, whereby the split gate typeflash semiconductor memory device is completed. According to theabove-mentioned publication, the split gate flash semiconductor memorydevice has enhanced programming and erasing efficiencies and improvedendurance in terms of its programmability and erasability.

[0009] Meanwhile, Japanese Laid-Open Patent Publication No. 1999-26616discloses a split gate type of memory device including an insulationlayer for a floating gate formed on a semiconductor substrate, aninsulation layer on the floating gate, a sidewall silicon oxide layercovering the sidewall of the floating gate, and a control gate insulatedfrom the floating gate by the insulation layer and the sidewall siliconoxide layer. In this split gate type of memory device, the floating gatecomprises polysilicon, and a silicon oxide layer is substituted for atleast a portion of the polysilicon near the sidewall of the floatinggate electrode. According to the publication, data writing and holdingcharacteristics of the split gate type of memory device are improvedwithout causing variations in the threshold voltage at the control gate,and data from being excessively erased.

[0010] However, in the methods described above, additional processes arerequired for forming the insulation layer between the floating gate andthe control gate, and the gates may not be precisely aligned. Therefore,problems still remain, such as excessive cell size and the difficulty ofintegrating the memory device with a logic device.

SUMMARY OF THE INVENTION

[0011] An feature of the present invention is to provide a method offorming a floating gate having enhanced electron discharging andinjecting efficiencies.

[0012] Another feature of the present invention is to provide a methodof manufacturing a non-volatile semiconductor memory device having afloating gate that is accurately aligned with a control gate.

[0013] In accordance with one aspect of the present invention, an edgeportion of a conductive pattern, constituting a floating gate, isprovided with a high degree of sharpness. To this end, first, aconductive layer is formed on a semiconductor substrate. Next, theconductive layer is patterned using a photolithographic process to forma conductive a pattern on the semiconductor substrate. Then, a firstinsulation layer is formed on a sidewall of the conductive pattern insuch a way that the sharpness of the edge portion of the conductivepattern is increased. Subsequently, a second insulation layer is formedat the upper portion of the conductive pattern so that the edge portionof the conductive pattern is even further increased.

[0014] In accordance with another aspect of the present invention, anunderlying structure including a first conductive pattern is formed on asemiconductor substrate. A first insulation layer is formed on asidewall of the first conductive pattern. Subsequently, a secondconductive pattern that will serve as a control gate is formed on thefirst insulation layer. Preferably, the second conductive pattern isformed by etching conductive material using a dry etching process. Then,a second insulation layer is formed on the second conductive pattern.

[0015] In accordance with still another aspect of the present invention,a first insulation layer and a first conductive layer are sequentiallyformed on a semiconductor substrate. Then, the first conductive layer isetched to pattern the same in a first direction. A second insulationlayer is formed on the etched first conductive layer. The firstinsulation layer and the etched first conductive layer are etched topattern the same in a second direction and thereby form a firstconductive pattern on the first insulation layer. A sidewall of thefirst conductive pattern is oxidized to form a first oxide layer on thesidewall of the conductive layer. A second conductive layer is formed onthe semiconductor substrate including over the first conductive patternand the second insulation layer. The second conductive layer is thenpatterned to form a second conductive pattern. Preferably, thepatterning of the second conductive layer is performed using a dryetching process. Subsequently, a source region is formed in thesemiconductor substrate adjacent the first conductive pattern. Then, thesecond insulation layer is etched away. An upper portion of the firstconductive pattern is oxidized to form a second oxide layer. Finally, adrain region is formed in the semiconductor substrate adjacent thesecond conductive pattern.

[0016] According to the present invention, the sharp edge portion of thefloating gate enhances the efficiencies of electron discharging andinjecting. In addition, the alignment between the floating gate and thecontrol gate is ensured by forming the control gate using a dry etchingprocess. Furthermore, the split gate type of flash semiconductor memorydevice of the present invention can be produced with a, a higher degreeof integration than a conventional flash semiconductor memory deviceresulted whose cell size is 2-Tr. Still further, the split gate type offlash semiconductor memory device of the present invention, when used ina logic circuit, facilitates a high speed reading and writing of datawithout consuming a large amount of power.

BRIEF DESCRIPTION OF THE DRAWINGS

[0017] These and other objects, features and advantages of the presentinvention will become more readily apparent by referring to thefollowing detailed description thereof made in conjunction with theaccompanying drawings.

[0018]FIG. 1 is a flowchart illustrating one embodiment of a method ofmanufacturing a floating gate according to the present invention;

[0019]FIGS. 2A to 2C are cross-sectional views of a substrate,illustrating the method of forming the floating gate of a non-volatilesemiconductor memory device according to the present invention asoutlined in FIG. 1;

[0020]FIG. 3 is a plan view of a non-volatile semiconductor memorydevice according to the present invention;

[0021]FIG. 4 is a flowchart illustrating another embodiment of a methodof manufacturing a non-volatile semiconductor memory device according tothe present invention;

[0022]FIGS. 5A to 5C are cross-sectional views of a substrate,illustrating the method of manufacturing the non-volatile semiconductormemory device according to the embodiment outlined in FIG. 4;

[0023]FIG. 6 is a flowchart illustrating still another embodiment of amethod of manufacturing a non-volatile semiconductor memory deviceaccording to the present invention; and

[0024]FIGS. 7A to 7K are cross-sectional views of a substrate,illustrating still another embodiment of a method of forming anon-volatile semiconductor memory device according to present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] The present invention now will be described more fullyhereinafter with reference to the accompanying drawings. Note, likereference numbers designate like elements throughout the drawings. Also,the relative thickness of layers may be exaggerated in the drawings forclarity in illustrating the present invention.

[0026]FIG. 1 outlines a first embodiment of a method of manufacturing afloating gate according to the present invention.

[0027] Referring to FIG. 1, a conductive layer of silicon (Si), e.g.,amorphous silicon, polysilicon, or silicon doped with impurities, isformed on a semiconductor substrate (step S11). Then, the conductivelayer is patterned using a photolithographic process to form aconductive pattern on the semiconductor substrate. Alternatively, theconductive layer may comprise a metal such as copper (Cu), tungsten (W),aluminum (Al), titanium (Ti), and the like.

[0028] Next, a first insulation layer is formed on a sidewall of theconductive pattern so that an edge portion of the conductive pattern hasa first sharpness (step S12). More specifically, the first insulationlayer is formed by oxidizing the sidewall of the conductive pattern.

[0029] Then, a second insulation layer is formed at an upper portion theconductive pattern so that the edge portion of the conductive patternbecomes even sharper (step S13). The second insulation layer is alsoformed by oxidizing the conductive pattern but this time at the upperportion thereof.

[0030]FIGS. 2A to 2C illustrate, in detail, the first embodiment of amethod of forming a floating gate of a non-volatile semiconductor memorydevice according to the present invention.

[0031] Referring to FIG. 2A, a conductive layer is formed on asemiconductor substrate 10. The conductive layer is patterned by aphotolithographic process to form a conductive pattern 20 on thesemiconductor substrate 10. The conductive pattern 20 constitutes anunderlying structure such as an electrode, a plug, a bit line or a wordline. Preferably, however, the conductive pattern 20 constitutes afloating gate of a flash semiconductor memory device.

[0032] When the conductive pattern 20 constitutes the floating gate of aflash semiconductor memory device, the conductive pattern 20 is formedof amorphous silicon, polysilicon or silicon doped with impurities by alow pressure chemical vapor deposition (LPCVD) process. When theconductive pattern 20 is formed using polysilicon, the conductivepattern 20 may have a polycide structure in which a metal silicide filmis formed on a polysilicon film. Alternatively, when the conductivepattern 20 is formed using polysilicon or amorphous silicon, theconductive pattern 20 may be doped with impurities by a PCl₃ diffusionprocess, an ion implantation process, or an in-situ doping process.

[0033] Also, an insulation layer comprising an oxide or nitride layermay be formed on the semiconductor substrate 10 before the conductivepattern 20 is formed. Then, the conductive layer is formed on theinsulation layer. In this case, the conductive layer is formed on thesemiconductor substrate 10 by a chemical vapor deposition (CVD) process,a physical vapor deposition (PVD) process or a sputtering process. Theconductive layer is patterned to form the conductive pattern 20 on theinsulation layer.

[0034] Referring to FIG. 2B, a first insulation layer 22 is formed on asidewall of the conductive pattern 20 by oxidizing only the sidewall ofthe conductive pattern 20. As a result, the edge portion 23 of theconductive pattern 20 becomes cuspate, subtending a first angle Θ1 witha vertical axis (an axis perpendicular to substrate 10). That is, thesidewall of the conductive pattern 20 becomes concave, whereby the edgeportion 23 of the conductive pattern 20 becomes more pointed, inaccordance with the formation of the first insulation layer 22 on thesidewall of the conductive pattern 20.

[0035] In the present embodiment, the first insulation layer 22 isformed on the sidewall of the conductive pattern 20 by merely oxidizingthe sidewall of the conductive pattern 20, i.e., without an additionalprocess such as a CVD process or a PVD process. More specifically, thefirst insulation layer 22 is formed by a simple thermal oxidationprocess or a local oxidation of silicon (LOCOS) process. As a result,the first insulation layer 22 is rounded to thereby form the cuspateedge portion 23 of the conductive pattern 20. The edge portion 23 thushas a first sharpness corresponding to the first angle Θ1.

[0036] Note, also, a nitride layer may be formed at an upper portion ofthe conductive pattern 20 as an oxidation blocking layer before thefirst insulation layer 22 is formed on the sidewall of the conductivepattern 20.

[0037] Referring to FIG. 2C, a second insulation layer 26 is formed atthe upper portion of the conductive pattern 20 by oxidizing the upperportion of the conductive pattern 20. The oxidizing process forms aconcavity in the upper portion of the conductive pattern 20 such thatthe second insulation layer 26 has a slightly rounded shape. As aresult, the edge portion of the conductive pattern 20 becomes even morecuspate, as designated by reference numeral 27, subtending a secondangle Θ2 with a horizontal axis (parallel to the substrate 10). That is,the edge portion 27 of the conductive pattern 20 attains a secondsharpness greater than that of the first sharpness.

[0038] In the present embodiment, the second insulation layer 26 isformed at the upper portion of the conductive pattern 20 by a thermaloxidation process or an LOCOS process, i.e., without a complexadditional process such as a CVD process or a PVD process.

[0039] Referring to FIG. 3, a non-volatile semiconductor memory deviceof the present invention includes an insulation region and activeregions, and a floating gate 220 and a control gate 320 disposed on bothsides of the insulation region. The direction A-A′ in FIG. 3 across thefloating gate 220 will hereinafter be referred to as the “firstdirection” while the direction B-B′ across the active regions and theinsulation region will be hereinafter referred to as the “seconddirection”.

[0040] According to the present embodiment, both the upper portion andthe sidewall of the floating gate are oxidized to form a sharp edgeportion. Thus, the edge portion of the floating gate is much sharperthan that of the conventional floating gate in which only the sidewallis oxidized. The sharper edge portion allows electrons to move moreefficiently from the floating to a control gate. Accordingly, thecharacteristics of a non-volatile semiconductor memory device employingthe floating gate of the present invention are enhanced.

[0041]FIG. 4 outlines a method of manufacturing a non-volatilesemiconductor memory device according the present invention.

[0042] Referring to FIG. 4, an underlying structure, including a firstconductive pattern, is formed on a semiconductor substrate (step S21).Then, a first insulation layer is formed on a sidewall of the conductivepattern (step S22).

[0043] Next, a second conductive pattern serving as a control gate isformed on the first insulation layer (step S23). Then, a secondinsulation layer is formed on the second conductive pattern (step S24).

[0044]FIGS. 5A to 5D illustrate in detail the method of manufacturingthe non-volatile semiconductor memory device according to the presentinvention. FIGS. 5A to 5D are each a sectional view as taken along lineB-B′ in FIG. 3.

[0045] Referring to FIGS. 3 and 5A, an underlying structure 40 includinga first conductive pattern 50, which corresponds to a floating gate ofthe non-volatile semiconductor memory device, is formed on a substrate30. Note, also, an underlying insulation layer 45 comprising an oxide ornitride layer may be formed between the substrate 30 and the firstconductive pattern 50. In that case, the underlying insulation layer 45is formed by a CVD process, a PVD process, or a sputtering process usingan oxide, a nitride or oxynitride.

[0046] The first conductive pattern 50 is formed of amorphous silicon,polysilicon, silicon doped with impurities or polysilicon having a metalsilicide formed thereon by an LPCVD process. The first conductivepattern 50 is produced by forming a first conductive layer (not shown)on the substrate 30, primarily etching the first conductive layer topattern the same in the first direction, and by then secondarily etchingfirst conductive layer to pattern the same in the second direction.

[0047] More specifically, after the first conductive layer is formed onthe substrate 30, an oxide layer (not shown) or a nitride layer (notshown) is formed on the first conductive layer to define the activeregion. A photoresist pattern is formed on the oxide layer or thenitride layer, and then the first conductive layer is patterned in thefirst direction using a photolithographic process. The patterning of thefirst conductive layer in the first direction prevents the active regionand the first conductive pattern corresponding to the floating gate frombeing misaligned. Subsequently, an insulation layer (not shown) isformed on the etched first conductive layer. Preferably, the insulationlayer comprises nitride. After a photoresist pattern is formed on theinsulation layer, the etched first conductive layer is patterned in thesecond direction using the photoresist pattern as an etching mask.

[0048] Referring to FIG. 5B, a first insulation layer 52 is formed on asidewall of the first conductive pattern 50. The first insulation layer52 is an oxide layer formed by oxidizing the sidewall of the firstconductive pattern 50, i.e., without an additional process such as a CVDprocess or a PVD process. More specifically, the first insulation layer52 is formed from the first conductive pattern 50 by a simple thermaloxidation process or a local oxidation of silicon (LOCOS) process. As aresult, the first insulation layer 52 is rounded, i.e., iscrescent-shaped. Accordingly, the sharpness of the edge portion of thefirst conductive pattern 50 is increased.

[0049] Referring to FIG. 5C, a second conductive pattern 60corresponding to a control gate of the non-volatile semiconductor memorydevice is formed on the first insulation layer 52. The second conductivepattern 60 is formed of a layer of amorphous silicon, polysilicon,silicon doped with impurities or polysilicon having a metal silicidethereon. The layer is then anisotropically etched (dry etched) topattern the same and thereby complete the forming of the secondconductive pattern.

[0050] According to the present embodiment, the second conductivepattern 60 is formed in the shape of a spacer by an anisotropic dryetching process. To this end, a plasma etching process or a reactive ionetching (RIE) process may be used. Unlike a photolithographic processwhose degree of resolution is limited, the dry etching process preventsa misalignment between the first conductive pattern 50 and the secondconductive pattern 60, thereby ensuring that the non-volatilesemiconductor memory deviceperforms well.

[0051] Referring to FIG. 5D, a second insulation layer 54 is formed onthe first conductive pattern 50. The second insulation layer 54 is anoxide layer formed by oxidizing an upper portion of the first conductivepattern 50. In particular, the second insulation layer 54 is formed atthe upper portion of the first conductive pattern 50 by a thermaloxidation process or an LOCOS process without a complex extra processsuch as a CVD process or a PVD process. Accordingly, the secondinsulation layer 54 is interposed between the first conductive pattern50 and the second conductive pattern 60. As a result, the edge portionof the first conductive pattern 50 becomes even sharper.

[0052] In this embodiment as well, both the upper portion and thesidewall of the first conductive pattern 50 are oxidized to increase thesharpness at the edge portion thereof. When the non-volatilesemiconductor memory device employs the first conductive pattern 50 as afloating gate, electrons migrate efficiently from the floating gate tothe control gate.

[0053] In the embodimentas described above, the second insulation layer54 is formed at the upper portion of the first conductive pattern 50 byoxidizing the upper portion of the first conductive pattern 50, afterthe second conductive pattern 60 is formed. Alternatively, the secondinsulation layer 54 may be formed before the second conductive pattern60 is formed on the first conductive pattern 50.

[0054]FIG. 6 outlines another method of manufacturing a non-volatilesemiconductor memory device according to the present invention.

[0055] Referring to FIG. 6, a first insulation layer and a firstconductive layer are formed sequentially on a semiconductor device (stepS30). Then, the first conductive layer is etched so as to be patternedin the first direction (step S31). Subsequently, a second insulationlayer is formed on the first conductive layer (step S32).

[0056] Next, the first insulation layer and the first conductive layerare etched so as to be patterned in the second direction to form a firstconductive pattern on the first insulation layer (step S33). A sidewallof the first conductive pattern is oxidized to form a first oxide layeron the sidewall of the first conductive layer (step S34).

[0057] A second conductive layer is then formed on the semiconductorsubstrate including over the first conductive pattern and the secondinsulation layer (step S35). The second conductive layer is patterned toform a second conductive pattern (step S36). After the second conductivepattern is formed, a source region is formed in the semiconductorsubstrate adjacent the first conductive pattern (step S37).

[0058] Next, the second insulation layer is etched (step S38). Then, theupper portion of the first conductive pattern is oxidized to form asecond oxide layer at the upper portion of the first conductive pattern(step S39). Subsequently a drain region is formed in the semiconductorsubstrate adjacent the second conductive pattern (step S40).

[0059]FIGS. 7A to 7K illustrate in more detail the method of forming thenon-volatile semiconductor memory device as outlined above. Morespecifically, FIGS. 7A to 7C are cross-sectional views of the substratetaken in the first direction in FIG. 3, and FIGS. 7D to 7K arecross-sectional views of the substrate taken in the second direction inFIG. 3.

[0060] Referring to FIG. 7A, a first insulation 110 and a firstconductive layer 200 are sequentially formed on a semiconductorsubstrate 100. The first insulation layer 110 is an oxide, nitride, oroxynitride layer, and the first conductive layer 200 comprisespolysilicon, amorphous silicon, silicon doped with impurities, orpolysilicon having a metal silicide thereon. The first conductive layer200 is formed by a CVD process, a PVD process or a sputtering process as

[0061] Referring to FIG. 7B, the first conductive layer 200 is etched soas to be patterned in the first direction. In particular, an oxide layer(not shown) or a nitride layer (not shown) is formed on the firstconductive layer 200. After a photoresist pattern is formed on the oxidelayer or the nitride layer, the first conductive layer 200 is patternedin the first direction by a photolithographic process. This preventsmisalignment in the first direction between the active region and thefirst conductive pattern 201 constituting the floating gate.

[0062] Referring to FIG. 3 and FIG. 7C, a second insulation layer 220 isformed on the first conductive pattern 201. Preferably, the secondinsulation layer 220 comprises a nitride, e.g., Si₃N₄, SiN_(x), SiONI.In particular, the second insulation layer 220 is formed by a CVDprocess, a plasma enhanced chemical vapor deposition (PECVD) process, aPVD process or a sputtering process.

[0063] Referring to FIG. 7D, the first insulation layer 110 and thefirst conductive pattern 201 are secondarily etched so as to bepatterned in the second direction. In particular, a photoresist patternis formed on the second insulation layer 220, and the first conductivepattern 201 and second insulation layer 220 are etched using thephotoresist pattern as a mask.

[0064] Referring to FIG. 7E, a sidewall of the first conductive pattern201 is oxidized to form a first oxide layer 240 on the sidewall of thefirst conductive pattern 201. Accordingly, an edge portion of the firstconductive pattern 201 has a slightly rounded shape at the sidewall ofthe first conductive pattern 201, whereby the sharpness of the edgeportion is increased. And, as with the embodiments described above, thefirst oxide layer 240 is formed by merely oxidizing the sidewall of thefirst conductive pattern 201, i.e., without a complex additional processsuch as a CVD process or a PVD process. That is, the first oxide layer240 is formed by a simple thermal oxidation process or an LOCOS process.Furthermore, the second insulation layer 220 functions as ananti-oxidant layer during the forming of the first oxide layer 240,preventing the upper portion of the first conductive pattern 201 fromoxidizing while allowing only the sidewall of the first conductivepattern 201 to be oxidized.

[0065] Referring to FIG. 7F, a second conductive layer 300 is formed onthe semiconductor substrate 100 including over the first conductivepattern 201 and the second insulation layer 220. The second conductivelayer 300 is advantageously formed by an LPCVD process and comprisespolysilicon, amorphous silicon, silicon doped with impurities orpolysilicon having a metal silicide thereon. The second conductive layer300 is etched to form a control gate of the flash semiconductor memorydevice.

[0066] Referring to FIG. 7G, a second conductive pattern 320 is formedin the shape of a spacer by etching the second conductive layer 300. Inparticular, the second conductive pattern 320 is formed by ananisotropic dry etching process. To this end, a plasma etching process,a reactive ion etching (RIE) process, may be used for forming the secondconductive pattern 320. A misalignment between the first conductivepattern 201 and the second conductive pattern 320 is prevented becausethe second conductive pattern 320 is formed by an anisotropic dryetching process, and not by a photolithographic process whose degree ofresolution is rather limited. In addition, the anisotropic dry etchingprocess removes part of the second conductive layer 300 to facilitatethe forming of a source region.

[0067] Referring to FIG. 7H, the source region 400 is formed in thesemiconductor substrate 100 adjacent the first conductive pattern 201.The source region 400 is formed by doping impurities into thesemiconductor substrate 100 using an ion implantation process.

[0068] Referring to FIG. 7I, the second insulation layer 220 on thefirst conductive pattern 201 is removed. To this end, the secondinsulation layer 220 is treated with an etching solution containingphosphoric acid (H₃PO₄) at a temperature of about 180° C.

[0069] Referring to FIG. 7J, a second oxide layer 260 is formed byoxidizing the upper portion of the first conductive pattern 201.Accordingly, the edge portion of the first conductive pattern 201becomes slightly rounded at the upper portion of the first conductivepattern 201, i.e., relative a horizontal direction or a directionparallel to the semiconductor substrate 100.

[0070] According to the present embodiment, both of the upper portionand the sidewall of the first conductive pattern 201 are oxidized toform a sharp edge portion where the sidewall and the upper portion ofthe first conductive pattern 210 meet. That is, the edge portion of thefirst conductive pattern 201 will be much sharper than that of theconventional floating gate. As a result, electrons will move moreefficiently from the floating to the control gate, thereby significantlyenhancing the characteristics of the non-volatile semiconductor memorydevice.

[0071] Referring to FIG. 7K, a drain region 420 is formed in thesemiconductor substrate 100 adjacent the second conductive pattern 320.The drain region 420 is formed by implanting impurities into thesemiconductor substrate 100 using an ion implantation process.

[0072] A wiring (not shown) and a drain contact (not shown) are formedat the upper portion of and adjacent the second conductive pattern 320by a silicidation process and a metallization process to complete theflash semiconductor memory device.

[0073] Compared to the conventional non-volatile semiconductor memorydevice, such as a stacked type of flash semiconductor memory device, thesplit gate type of flash semiconductor memory device manufacturedaccording to the method of the present invention is less prone toproblems such as over-erasing and high power consumption in a datawriting mode. Also, the split gate type of flash semiconductor memorydevice can be manufactured according to the present invention to have alower integration density than a conventional flash semiconductor memorydevice having a cell size of 2-Tr. Furthermore, the split gate type offlash semiconductor memory device of the present invention can bereadily integrated with a logic circuit to produce a device that canread and write of data, at a high speed and yet consume a relatively lowamount of power in doing so.

[0074] Finally, although the present invention has been described inconnection with the preferred embodiments thereof, the present inventionis not so limited. Rather, various changes to and modifications of thepreferred embodiments are seen to be within the true spirit and scope ofthe present invention as hereinafter claimed.

What is claimed is:
 1. A method of manufacturing a floating gate,comprising: forming a conductive pattern on a substrate, wherein theconductive pattern has a sidewall, an upper portion, and an edge portionwhere the upper portion and sidewall meet; forming a first insulationlayer on the sidewall of the conductive pattern in a way that increasesthe sharpness of the edge portion of the conductive pattern; and forminga second insulation layer on the upper portion of the conductive patternin a way that increases the sharpness of the edge portion.
 2. The methodof claim 1, wherein said forming of the conductive pattern comprisesforming a layer of polysilicon on the substrate.
 3. The method of claim1, wherein said forming of the conductive pattern comprises forming alayer of silicon on the substrate, and doping the silicon withimpurities.
 4. The method of claim 1, wherein said forming of theconductive pattern comprises forming a layer of polysilicon on thesubstrate, and forming a metal silicide on the polysilicon.
 5. Themethod of claim 1, wherein said forming of the first insulation layercomprises forming an oxide layer on the sidewall of the conductivepattern.
 6. The method of claim 5, wherein the first insulation layer isformed by oxidizing the conductive pattern.
 7. The method of claim 1,wherein said forming of the second insulation layer comprises forming anoxide layer on the upper portion of the conductive pattern.
 8. Themethod of claim 7, wherein the second insulation layer is formed byoxidizing the conductive pattern.
 9. A method of manufacturing anon-volatile semiconductor memory device, comprising: forming a floatinggate on a substrate, the floating gate comprising a first conductivepattern having a sidewall, an upper portion, and an edge portion wherethe upper portion and sidewall meet; forming a first insulation layer onthe sidewall of the first conductive pattern; forming a control gate onthe first insulation layer and the first conductive pattern, the controlgate comprising a second conductive pattern; and forming a secondinsulation layer on the upper portion of the first conductive pattern soas to be located between the first conductive pattern and the secondconductive pattern.
 10. The method of claim 9, wherein said forming thefirst conductive pattern comprises: forming a conductive layer on thesubstrate, etching the conductive layer on the substrate to pattern theconductive layer in a first direction, and subsequently etching theconductive layer to pattern the conductive layer in a second directionperpendicular to the first direction.
 11. The method of claim 10,wherein each said etching of the conductive layer is performed by aphotolithographic process.
 12. The method of claim 9, wherein saidforming a floating gate comprises forming an underlying insulation layeron the substrate, and forming the first conductive pattern on theunderlying insulation layer.
 13. The method of claim 9, wherein saidforming of the first insulation layer comprises forming an oxide layeron the sidewall of the first conductive pattern.
 14. The method of claim13, wherein the first insulation layer is formed by oxidizing the firstconductive pattern.
 15. The method of claim 9, wherein said forming thesecond conductive pattern comprises: forming a conductive layer on thefirst insulation layer and the first conductive pattern, and dry etchingthe conductive layer.
 16. The method of claim 9, wherein said forming ofthe second insulation layer comprises forming an oxide layer on theupper portion of the first conductive pattern.
 17. The method of claim16, wherein the second insulation layer is formed by oxidizing the firstconductive pattern.
 18. A method of manufacturing a non-volatilesemiconductor memory device, comprising: sequentially forming a firstinsulation layer and a first conductive layer on a substrate; etchingthe first conductive layer to pattern the first conductive layer in afirst direction; forming a second insulation layer on the etched firstconductive layer; forming a first conductive pattern by etching thefirst insulation layer and the etched first conductive layer so as topattern the first insulation layer and the etched first conductive layerin a second direction; forming a first oxide layer by oxidizing asidewall of the first conductive pattern; forming a second conductivelayer on the substrate including over the first conductive pattern andthe second insulation layer; forming a second conductive pattern byetching the second conductive layer; forming a source region in thesubstrate adjacent the first conductive pattern; etching the secondinsulation layer from atop the first conductive pattern; forming asecond oxide layer by oxidizing an upper portion of the first conductivepattern; and forming a drain region in the substrate adjacent the secondconductive pattern.
 19. The method of claim 18, wherein said forming ofthe second conductive pattern comprises a dry etching process.
 20. Themethod of claim 19, wherein said forming of the source region and thedrain region comprises an ion implantation process.